The following article appears in the journal JOM, 51 (3) (1999), pp. 22-27.

Materials Issues in Area-Array Microelectronic Packaging

TABLE OF CONTENTS
INTRODUCTION THE MATERIALS CHALLENGE OF ELECTRONIC PACKAGING CRITICAL MATERIALS AND PROCESSING ISSUES Packaging Devices with Copper Metallization with a Low- Dielectric Fine-Pitch Packaging Organic Substrates Underfill Solder Reliability Radiation-Induced Soft Errors Lead-Free Solder Alloys FUTURE OUTLOOK References

The important issues in advanced area-array electronic packaging for semiconductor devices are materials driven. Some of the processing-driven materials issues include the effect of introducing a silicon device interface with copper pads and a low- dielectric, the effect of decreasing pitch and feature size on the package interconnects, the development and implementation of organic substrates, and advanced underfills for fine-pitch flip-chip applications. From a materials reliability aspect, important materials issues include enhanced solder interconnect reliability, -particle-induced soft errors, and the introduction of lead-free solder alloys.

INTRODUCTION

In the past, advances in silicon semiconductors had little or no effect on the electronic-package design or process. New advances in silicon devices have driven increases in chip speed, device density (e.g., the number of transistors/mm²), and power dissipation. These changes, and those planned in the future, require larger numbers of interconnects to and from the devices, improved electrical performance, more effective thermal management, software systems to design and model the assembly, and different sets of materials to make these changes happen. Furthermore, the package is shrinking to a minimalist version of the products that traditionally have been called packaging. The chip and board have become a conjugate packaging system that must provide the traditional levels of electrical, mechanical, thermal interfaces, and environmental protection, with the additional challenge of increased performance.¹ In addition, the boundary between where the device ends and where the package begins has become blurred with passive devices (e.g., resistors, capacitors, etc.) in the package and redistribution layers that act as space transformers on the chip. Electronic packaging is becoming one of the greatest challenges in manufac-turability, performance, and reliability in advanced electronics applications.

Some of the needs for improved performance can be met with some version of the packaging solutions that have been developed over the last 5-10 years. These solutions have typically focused on peripheral packages with wirebond chip-to-package interconnects. A schematic illustration of one such package is shown in Figure 1. The devices on the silicon die are routed from the center location on the chip to the wirebond pads on the periphery. The chip is mechanically bonded to a substrate and is gold-wirebonded to electrically connect the chip to the leadframe. The leadframe fans interconnects through a dielectric (ceramic or organic) into a peripheral pattern, where it can be soldered to a printed wiring board. As the number of leads increases, this type of package becomes problematical. The minimum wirebond pitch (the distance from the center of one wirebond lead to the center of another) is currently 70 mm, with a decrease to 50 mm expected in 1999.²

Figure 1. An isometric-section schematic that illustrates a peripheral package showing a dual-in-line-package (DiP) that is wirebonded.

An alternative to peripheral interconnect packaging is to access the unused area under the chip and package for interconnects in an area-array solution. A schematic example of an area-array package is shown in Figure 2. In area-array packaging, the surface of the chip has an array of solder interconnects (solder bumps) that are joined to a substrate when the chip is flipped over (flip-chip packaging).³ The interconnects can then be fanned-out through the package to another area-array geometry on the bottom of the package called a ball-grid array (BGA).⁴ An organic underfill fills the gap between the silicon die and substrate to enhance mechanical adhesion. The pitch of the solder bumps is much coarser than for wirebonding-200 µm to 250 µm.

One of the great advantages of the area-array package is an increase in the number of available input/output (I/O) leads over peripheral designs. For example, at a 70 µm pitch, the maximum number of wirebonds on a 10 mm chip is less than 600. For an area-array package on the same 10 mm chip, even at the coarser bump pitch of 250 µm, the number of available I/O interconnects increases to 1,600.

Furthermore, it is difficult to design the sweep of wires from the chip to the leadframe in peripheral packaging to eliminate shorts and minimize inductance between adjacent wires. These issues are not present in the much coarser pitched area-array package. In a flip-chip package, the solder interconnects can also act as heat sinks because they are attached to the active surface of the silicon and are massive enough to draw heat away from the silicon.

Figure 2. A schematic of an area-array package with a flip-chip device interconnect and a ball-grid array package.

Finally, the cost of current peripheral array solutions have generally exceeded customer targets while falling short of advanced requirements in performance and reliability. Additional development is needed to meet the target of reduced cost with increasing functionality and performance. This cost/performance tradeoff is summarized in Figure 3. The number of pins, or I/O interconnects, must increase dramatically with functionality while the cost per pin must decrease at a rate comparable to that of the silicon device. Figure 3 also shows that future package feature size scales with silicon feature size (e.g., a 150 µm package feature scales with a silicon feature of 150 nm).

The requirements for improvements in the functionality of electronic devices will also drive an area-array package solution. High-performance applications have an I/O range of 1,000-2,000 with a voltage drop power requirement and ground availability in the middle of the chip, rather than at the edges, which results in a drive toward a flip-chip area-array solution. Hand-held (e.g., cellular telephones) and cost-performance (e.g., desktop and portable computers) applications have a lower I/O requirement, with a form factor that requires a tighter density of I/Os provided by an area-array package.

Even with the advantages created by area-array packaging, performance, reliability, and cost requirements are challenging currently available area-array electronic package design. The majority of these challenges are materials driven.

THE MATERIALS CHALLENGE OF ELECTRONIC PACKAGING

Figure 3. The assembly and packaging challenge. (Derived from the The National Technology Roadmap for Semiconductors Technology, 1997 edition, published by SIA).2

Consider a generic example of the processes and materials required to manufacture an area-array package. Deposition of metal on the aluminum or copper pads on the silicon device is used to provide a solder wettable surface for the flip-chip solder interconnects and a diffusion barrier to the silicon (Figure 4). The metals are deposited in an area array at the wafer level and can be plated or deposited by physical means (evaporating or sputtering). The metal stack, or under bump metallurgy (UBM), typically consists of an adhesion layer to the pad (chromium, titanium, or zincated aluminum), a diffusion barrier (chromium or nickel), and a solder wettable layer (nickel, copper, or gold). These layers are typically a few thousand angstroms thick and are patterned on the wafer by photolithography. Solder is deposited on the UBM by evaporation (high-lead-content solders), plating, or solder paste.

The flip-chip solder interconnects are typically a high-lead-content solder alloy (e.g., Pb-5Sn or Sn-3.5Pb, in wt.%) that has a melting point in excess of 300°C. This high-melting-temperature solder alloy does not reflow during subsequent soldering processes (e.g., substrate to board reflow). The solder is reflowed to form solder balls, and the wafer is then diced. For assembly into a package, the silicon die is soldered to a ceramic, or organic, substrate. A silica-filled anhydride resin underfill is then flowed and cured under the die to enhance mechanical adhesion. The substrate is patterned to mirror the configuration of the solder balls on the die. The substrate pads are metallized to be wettable by the solder. The substrate acts to redistribute the leads to a coarser pitch on the BGA side.

To form the BGA interconnects, solder balls are mechanically placed on the substrate lands using mechanical fixtures. The solder alloy for the BGA interconnects is typically a near eutectic Sn-Pb alloy that melts at 183°C. The balls are fluxed and reflowed to join to the substrate. Welding, or brazing, or glass sealing a lid on the die or by flowing and curing an organic encapsulent (glob top) over the die completes the package. The package is then ready for assembly to a printed wiring board.

CRITICAL MATERIALS AND PROCESSING ISSUES

Figure 4. A cross-section schematic of a UBM and solder bump for a flip-chip interconnect.

Packaging Devices with Copper Metallization with a Low- Dielectric

The devices for which copper and low- dielectric are the most suitable also require area-array packaging, involving flip-chip interconnects, in order to accommodate the large number of I/Os expected with these devices. The flip-chip array also reduces cross talk that could occur in wirebonded packages, because the long wires can act as antennas and create an inductive current in nearby conductors.

The move toward the use of copper and low on the die could potentially affect the manufacturability and reliability of the packaged devices. The significant issues involved in packaging copper and low k involve bonding with the copper and structural stability of the dielectric during processing and in service. Many of the currently used low- materials have properties that degrade at processing temperatures in excess of 250°C due to extensive cross-linking in the polymer. Therefore, the solders that must be used to interconnect with the copper/low- silicon device must have a suitable process temperature. The solder alloy proposed for this application is the near eutectic Sn-Pb alloy that melts at 183°C.

Figure 5. Process steps to fabricate a dual damascene structure with copper and a low- dielectric. (Adapted from Hu and Harper.)7 SiN and low- dielectric deposition; via definition by etch; pad definition by etch; barrier (e.g., tantalum) seed (Cu) physical vapor deposition; and copper plating and chemical-mechanical polishing.

There are a number of challenges associated with this proposed change. The UBM must be redeveloped in changing from a high-lead solder to the eutectic sol-der alloy. The greater amount of tin (~63 wt.%) in the eutectic solder alloy results in a much faster reaction with the wettable UBM metallization and could result in dewetting if the appropriate metal types and thicknesses are not present. The UBM metals are deposited in what could be highly stressed conditions that could affect the performance and reliability of the bumps.

These UBM structures were optimized for aluminum pad metallizations and may require changes for adhesion to copper pads. One metallization that has seen a great deal of development over the last few years and has shown a great deal of promise is electroless Ni-P. Electroless Ni-P has the advantage that it only plates over metal and, so, is a selective-metal-deposition technique as opposed to evaporation or sputtering, which require patterning and etching process steps. Electroless nickel has potential as a low-cost UBM and has a very slow reaction rate with tin. However, implementation of the electroless nickel as a UBM is not widespread because processing and reliability require further characterization efforts, but there are significant R&D efforts underway. Furthermore, electroless nickel is typically preceded by zincation on aluminum pads, which can not be performed on copper. A new process will need to be developed.

Fine-Pitch Packaging

There are a number of materials and processing challenges associated with finer pitches. As the pitch shrinks, the methods to deposit the solder become more limited. Solder paste is very difficult to deposit using a silk-screen method at pitches below 150 µm due to rheological limitations of forcing a semi-solid (the paste) into small holes (the silk screen). Evaporation is difficult because developing a metal screen mask with the required tolerances is prohibitively expensive. Solder plating is still a good option, but the solder must be very uniform across each die. Solder ball uniformity is critical because large variations between die could result in electrical opens for small balls and shorts for large balls (Figure 6).

Figure 6. The uniformity of ball size on the flip chip is important. (a) If the ball is undersized, electrical opens occur. (b) If the ball is oversized, electrical shorting is possible.

An additional issue with a decrease in ball size is the joint gap between the substrate and the die decreases to the point that it may become very difficult to flow underfill completely under the die. At 100 µm pitch, the gap between the die and substrate could be significantly less than 25 µm, the limit of underfill flow. For these very fine-pitch applications, an alternative underfill technique will need to be developed or flow under the chip will not be possible. One alternative would be to deposit the underfill material on the wafer immediately after flip-chip solder bumping. New underfill materials and processes would have to be developed to implement this process.

Organic Substrates

The move to an organic substrate is the focus of an extensive development effort worldwide. The board interconnect density for flip-chip substrates must accommodate the increasing density of off-chip interconnect, and cost-effective substrate capability that combines the necessary fine line and micro-via features must be developed. Micro-vias are the metal-filled holes that provide a conduction path between copper lines in the multiple layers of an organic substrate. Micro-via capability must also scale with line width/spacing in order to provide the "via in-line" structures necessary to support bump-pitch densification. At current 250 µm pitches, micro-vias can be created using a photolithographic process. At finer pitches, laser-drilling techniques must be developed to create the required small via size.

Advanced substrates for flip chips must also provide increased wireability while delivering improved electrical performance with reliability levels at least equivalent to current surface-mount applications. New materials with dielectric constants approaching 2.0 and with coefficients of thermal expansion approaching 6.0 ppm/°C will be necessary to meet fine-pitch requirements. Furthermore, uniformity and flatness are critical for organic substrates to ensure uniform joint size and bonding across each die as the interconnect pitch decreases.

The change in substrate materials drives the need for a lower melting temperature solder to replace the high-lead-content Sn-Pb alloys that are processed in excess of 300°C for ceramic substrates. The organic materials in a substrate are typically epoxy-based and char or burn at temperatures in excess of 250°C. The most common solder alloy candidate is near-eutectic Sn-Pb that can be processed at 200°C. However, this could result in a situation where the flip-chip interconnect melts every time an additional solder reflow occurs during subsequent processing. Multiple reflows of the solder interconnects accelerates intermetallic growth between the tin of the solder and the metallized pads for the UBM and substrate. One way to circumvent this issue is to deposit low-melting-temperature eutectic Sn-Pb solder on the substrate lands or on the high-melting-temperature solder bump. Reflow to the substrate can be performed at eutectic Sn-Pb soldering temperatures, but the mixing between the high-lead-content and eutectic solder results in a higher melting temperature composition. Subsequent re-flows at eutectic Sn-Pb processing temperatures will not remelt the composite alloy flip-chip joint. This addresses the low-temperature processing requirements for organic substrates, but does not address the low- dielectric low-temperature processing requirements because the high-lead-content solder must still be reflowed on the silicon die.

Underfill

Figure 7. An SEM micrograph of a flip-chip solder bump with silica-filled underfill. (Photograph courtesy of K.N. Tu at the University of California-Los Angeles.)

Without this underfill material the difference in the coefficient of thermal expansion between the chip (3 X 10^-6 mm/mm°C) and the substrate (~17 X 10^-6 mm/mm°C) would quickly result in fracture of the solder interconnects when variations in temperature occurred. New underfills must be developed to accommodate increased bump density and shrinking bump height. As bump density increases and pitch decreases, the underfill must flow into smaller and smaller spaces. The currently used 250 µm pitch requires an underfill with a thickness of 110 µm. At a 150 µm pitch, the dimension between the chip and substrate will be less than 50 µm but must result in 100 percent fill for required levels of reliability. Traditional flow dispensing and cure may not be suitable in these thin spaces due to a lack of capillary driving force. For very thin fill spaces, wafer-level deposition of the underfill will need to be developed. This wafer-level deposition would involve spin-on of an uncured polymer to a uniform thickness slightly less than the bump height. The wafer would then be diced and die-mounted on substrates. Reflow would form the solder joints and cure the underfill simultaneously. Materials development is required to create a filled polymer that can be spun to a uniform thickness of 25 µm or less, bonds well with silicon and substrate materials, and is compliant.

Solder Reliability

Under thermal cycling conditions, the solder interconnects undergo microstructural evolution through heterogeneous coarsening and failure that results in electrical opens.⁹ This situation is alleviated, although not eliminated, through the use of the underfill for the flip-chip interconnects. Currently, BGA interconnects are not underfilled because they are much more massive and typically join materials with more closely matched coefficients of thermal expansion. As the pitch shrinks and the die size increases, the amount of strain imposed upon the solder interconnects also increases. The strain imposed on the solder joints follows the relation

= Ta/h

where is the shear strain imposed, is the difference in coefficient of expansion between the joined materials, T is the temperature change, a is the distance from the neutral expansion point of the joined materials, and h is the thickness of the interconnect.

An example of the change in strain follows: For the 250 µm pitch, a die of 17.3 mm² has a = 8.65 mm and h = 110 µm; for 100 µm pitch, the die is 22.8 mm² with a = 11.4 mm and h = 25 µm (numbers are taken from Reference 2). The temperature excursion is 100°C and the die is Si (6 X 10^-6/°C) with an FR-4 substrate (17 X 10^-6/°C). The resultant shear strains in the outermost solder interconnects at 250 µm and 100 µm pitch are eight percent and 50 percent, respectively. The larger strains result in more rapid fatigue failures in both the solder and potential fractures in the silicon if the underfill transfers the strain to the more brittle component.

This issue may need to be addressed with more compliant interconnects and underfill with more fatigue-resistant interconnects. Another potential solution is to use greater standoff solder interconnects with an aspect ratio much greater than one. This solution has been incorporated with great success on BGA interconnects using column grid arrays¹⁰ rather than standard balls.

Radiation-Induced Soft Errors

The most significant emissions of alpha particles was from the lead in the solder interconnects. These radioactive sources are particularly insidious because the solder interconnects are located close to the silicon device and there are no barriers to absorb the particles. Lead and tin-lead alloys (solder) contain radioactive daughter elements of uranium and thorium that decay to form -particles. The principle cause of alpha emission is ²¹⁰Pb (an unstable isotope found in lead) that decays by - and -particles (-particle energy = 3.72 MeV) to form ²¹⁰Bi (decays with - and -particles [3.72 MeV]) and then the very unstable isotope of ²¹⁰Po, which subsequently decays with an -particle with an energy of up to 5.4 MeV.

As an example, a 5 MeV -particle penetrates into 25 µm of silicon and subsequently creates 1.4 X 10⁶ electron/hole pairs that can easily affect the charge state in a silicon device. The half life of ²¹⁰Pb is 21 years, and ²¹⁰Bi has a half life of 5.01 days. The half life of ²¹⁰Po is 138.4 days, but there is a continuing accumulation of ²¹⁰Po from the decay of the ²¹⁰Pb. Commonly used lead for solders can have -activity as large as 1.0 /cm²-h.

Soft errors can become more predominant as gate size shrinks and the subsequent charge area in the silicon that results in memory decreases. Therefore, there is a need for a source of lead with a low -radiation rate to limit the possibility of soft errors. Some sources of lead ore have lower -radiation levels, but these are often contaminated during the smelting, handling, and processing steps. Low -Pb ore has an activity on the order of 0.02 /cm²-h.¹¹ Since the half life of ²¹⁰Po is 22 years, extremely old lead would not be expected to have a large -activity. For example, lead recovered from sunken Spanish galleons and old Roman ship anchors has an -activity of less than 0.001 /cm²-h.¹¹ However, there is a very limited supply of this material. A newly proposed source (Pure Technologies) of low -Pb uses laser-isotope separation to refine lead to a state where -particle generation is drastically reduced to less than 0.0001 /cm²-h.¹¹

It should be noted that cosmic radiation is also a source of alpha particles. At sea level, the cosmic radiation levels are on the order of 0.005 /cm²-h and dramatically increase with altitude. Cosmic radiation issues typically have been addressed through designs that increase the radiation hardness of the device. However, device engineers must be aware that it is difficult, if not impossible, to reduce the -radiation level below cosmic levels through materials changes.

Lead-Free Solder Alloys

A number of tin-based solder alloys have been proposed as lead-free substitutes for packaging applications.¹³ There are no "drop-in" candidate alloys to replace eutectic Sn-Pb solder, but there are three alloys that stand out as strong possibilities for implementation as lead-free alternatives. These lead-free alloys, their melting behavior, and a brief discussion of their microstructure is given in Table II.

From a mechanical properties perspective, these lead-free alloys exhibit a higher yield strength and slower creep deformation than eutectic Sn-Pb. However, the alloys are susceptible to interfacial delamination at the intermetallic/solder interface under tensile loading conditions.¹⁵ These lead-free alloys also have better fatigue performance than eutectic Sn-Pb, with the Castin^TM alloy having the longest thermomechanical fatigue life.

FUTURE OUTLOOK

In the past, the electronic package did not limit the performance of silicon devices. As the devices become faster and more powerful, the package can be the roadblock to desired functionality. Future device development must be a fully integrated approach between device design, device processing, and packaging to meet advanced performance requirements.

References
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10. T. Caulfield et al., Ball Grid Array Technology, ed. J.A. Lau (New York: McGraw-Hill, 1995), p. 131.
11. R. Brodzinski, "A White Paper on Alpha Activity in Lead" (Richland, WA: Battelle Northwest, 1998).
12. U S. Congress, Senate: Lead Exposure Reduction Act of 1994. DEC. 401 (1994).
13. NCMS Lead-Free Solder Project Final Report (Ann Arbor, MI: National Center for Manufacturing Sciences, 1997).
14. F.G. Yost, F.M. Hosking, and D.R. Frear, eds., The Mechanics of Solder Alloy Wetting and Spreading (New York: Van Nostrand Reinhold, 1993).
15. D.R. Frear and P.T. Vianco, Metall. Tran A, 25A (1994), p. 1509.

ABOUT THE AUTHOR

Darrel R. Frear earned his Ph.D. in materials science at the University of California at Berkeley in 1987. He is currently manager of the low-cost flip-chip project at Sematech. Dr. Frear is also a member of TMS.

For more information, contact D.R. Frear, Motorola, Semiconductor Product Systems, MD-EL725, 2100 East Elliot Road, Tempe, Arizona 85284; telehone (602) 413-6655; fax (602) 413-4511; e-mail r46897@email.sps.mot.com.