8:20AM, N1+
"High Field Transport in Non-Stoichiometric GaAs:" J.P. IBBETSON*, P.J. Corvini, J. Bowers, U.K. Mishra, Center for Non-stoichiometric III-V Compounds (supported by AFOSR), Dept of Electrical and Computer Engineering, Box 47, *Materials Dept., University of California, Santa Barbara, CA 93106
Due to its semi-insulating nature, non-stoichiometric (NS) GaAs grown at low substrate temperature by molecular beam epitaxy is often used for applications that involve high electric fields. However, the large trap densities that are responsible for its semi-insulating nature also afford the possibility of unusual current-voltage behavior. In particular, we have observed a pronounced current saturation in NS-GaAs grown and annealed at various temperatures.
The onset of the current saturation regime (CSR) occurs at a field of ~ 10k V/cm and the CSR can extend over an order of magnitude in voltage. This behavior can be attributed to drift velocity saturation in the presence of a large number of electron traps. In broad terms, the quasi-Fermi level is unable to move without a prohibitively large change in the local trapped space-charge (so-called "pinning"). However, once the electron drift velocity saturates the current can increase only by increasing the free electron concentration. To do so, the quasi-Fermi level must move towards the conduction band, filling traps as it moves. Thus, a large increase in the space-charge occurs for a small change in the current, leading to the observed saturation.
The CSR can be observed for a limited range of trap densities in which all of the following conditions are met: (1) trap compensation;. (2) the trap densities are sufficiently high that filling initially empty traps results in a field larger than that required for velocity saturation; (3) the trap densities are sufficiently low that hopping conduction is negligible compared to free electron conduction. In NS-GaAs, the trap densities are known to be a strong function of the growth temperature and the anneal temperature and so we have measured the high field behavior in several samples. For the lowest growth temperatures (200-250deg.C) saturation is observed only when the samples are annealed above 650deg.C. For NS-GaAs grown at 350deg.C, the saturation is observed in the as-grown sample and following anneals at > 600deg.C. No saturation is observed for an intermediate anneal at 550deg.C, however, due to the "appearance" of hopping conduction. Thus, the current-voltage behavior is a useful characterization tool for NS-GaAs.
An analytical model has also been developed on the basis of space-charge-limited transport theory assuming a simple two-section velocity-field characteristic and deep donors weakly compensated by shallow acceptors. Experimental results are compared with the theory.
8:40AM, N2
"Stability of a Low-Temperature Grown GaAs Surface Layer Following Air Exposure:" D.B. JANES, School of Electrical and Computer Engineering, D. McInturff, J.M. Woodall, School of Electrical and Computer Engineering and NSF MRSEC for Technology Enabling Heterostructure Materials, 1285 EE Bldg, S. Hong, R. Reifenberger, Department of Physics, 1396 Physics Bldg., Purdue University, West Lafayette, IN 47907
Low-temperature grown (LTG) GaAs, i.e., GaAs layers grown at low temperatures (250-300deg.C) by molecular beam epitaxy (MBE), possesses a number of interesting electronic and structural properties which can be associated with the 1% to 2% excess arsenic incorporated into the lattice. In unannealed material, the excess arsenic is primarily in antisites and interstitials. Scanning tunneling microscopy (STM) performed on LTG:GaAs layers exposed by in-situ cleaving in ultra high vacuum (UHF) has shown a band of midgap statesassociated with the high density of antisite defects. Of particular interest for electronic and optoelectronic devices is the very short carrier lifetime resulting from the high defect density. Recently, a structure consisting of a heavily doped layer capped with a thin (3 - 10 nm) LTG:GaAs surface layer has been used to achieve ex-situ low-resistance, nonalloyed ohmic contacts to n type GaAs. The conduction model for the contact structure consisted of defect assisted tunneling through the LTG:GaAs layer and tunneling through the narrow space charge region in the heavily doped layer. The stability of the LTG:GaAs following air exposure was not addressed. In fact, the formation of a native oxide layer comparable to that formed on unpassivated GaAs surfaces was presented as a possible explanation for the dependence of specific contact resistivity on LTG:GaAs layer thickness.
In this work, we demonstrate the stability of a LTG:GaAs surface layer by STM spectroscopy performed after the sample has been exposed to atmosphere. These studies resolve the band of midgap states associated with antisite defects in the surface layer and indicate that the LTG:GaAs surface layer does not oxidize significantly during brief exposure to air, in contrast to other unpassivated GaAs surfaces. The inhibition of surface oxidation is associated with the low concentration of holes arising from the short carrier lifetimes in the LTG:GaAs layer. These results are used to verify the model previously proposed for conduction in the unannealed contact structures incorporating a LTG:GaAs surface layer.
The GaAs layer structure consisting of a thin (10 nm) layer of low-temperature-grown GaAs (LTG:GaAs) on a heavily n-doped GaAs layer, both grown by molecular beam epitaxy. The sample was exposed to the atmosphere for periods up to 24 hours between the layer growth and STM characterization. Tunneling spectroscopy performed in an ultra-high-vacuum (UHV) STM system shows both the GaAs band edges and a band of midgap states associated with the excess As in the LTG:GaAs layer. The features of the STM I-V curves following air exposure, namely the observation of the midgap states and the absence of Schottky characteristics near zero bias between tip and substrate, indicate that the LTG:GaAs layer does not oxidize rapidly.
This work is supported in part by the NSF MRSEC program under Grant 9400415-DMR and the Army Research Office URI program under Contract DAAL03-92-G-0144.
9:00AM, N3+
"Interfacial Barrier of LTG-Al0.3Ga0.7As Epitaxial Passivation in GaAs FETs:" N.X. NGUYEN, J.P. Ibbetson, U.K. Mishra, Electrical and Computer Engineering Department, University of California at Santa Barbara, Santa Barbara, CA 93106
Surface passivation of GaAs in device application is still an unresolvedproblem that leads to high cost and low reliability. While SiNx is an effectiveenvironmental passivant (preventing the change of the surface properties due to environmental factors such as oxidation and humidity), it is not an electrical passivant. Therefore an epitaxial passivation technology that could electronically decouple the free surface from the active channel is verydesirable. The passivating materials should also have a high sheet resistivity and a low interfacial barrier to the active channel to minimize the charge depletion and parasitic resistances. We have discovered that LTG-Al0.3Ga0.7As satisfied the above criteria as a passivation layer in high performance GaAs power FETs. While similar to reported passivation with LTG-GaAs in that it substantially improved the breakdown voltage of the device, LTG-Al0.3Ga0.7As also has an additional beneficial property of a low interfacial barrier.
LTG-Al0.3Ga0.7As materials growth and processing that produces the desirable low interfacial barrier with GaAs are systematically investigated. The interfacial potential (or work function difference) between LTG-Al0.3Ga0.7As and GaAs can be inferred by the resultant depletion of carriers in GaAs. This is effectively monitored by Van der Pauw measurements. The structure was grown by MBE and consisted of a d-doped layer with sheet charge of 1.4x1012 cm-2. This is followed by 500Å of undoped GaAs, 200Å of AlAs and 50Å of GaAs all grown at 590deg.C. Next, the temperature was lowered to 270deg.C for growth of LTG-Al0.3Ga0.7As, capped with 50Å of LTG-GaAs. The purpose of the AlAs barrier is to prevent back diffusion of As and associated defects. The 50Å GaAs layer prevents contamination of the AlAs during the cool-down and presents a clean surface for LTG-Al0.3Ga0.7As growth. The samples were then annealed ex-situ using a rapid thermal annealer from 425deg.C to 650deg.C in 25deg.C steps. Van der Pauw measurements of the sheet charge were performed at each temperature. The interfacial barriers were deduced from the measured sheet charge.
Similar to LTG-GaAs, the interfacial barrier between LTG-Al0.3Ga0.7As and the active channel increased monotically from 425C to 575deg.C as a function of annealing temperatures. However, at 600deg.C, a lowering of the interfacial barrier was observed. Upon annealing at higher temperature, the barrier again raised back up. This has never been observed in LTG-GaAs passivation. There are also evidences that the magnitude of the change is strongly influenced by the growth and annealing ambient of the samples. In addition, we also have fabricated 1 um FETs with LTG-Al0.3Ga0.7As passivation and observed record low frequency noise performance, supporting the hypothesis that LTG-Al0.3Ga0.7As would decouple the free surface from the active channel. These combined properties demonstrated the potential of LTG-Al0.3Ga0.7As as an electronic passivant for GaAs devices.
9:20AM, N4
"Dominant Deep Level and Its Photocapacitance Quenching in LT-GaAs Grown by MBE:" SHUNSUKE SHIOBARA, Tamotsu Hashizume, Hideki Hasegawa, Research Center for Interface Quantum Electronics, and Graduate School of Electronics and Information Engineering, Hokkaido University, Sapporo 060, Japan
Undoped GaAs layers grown by molecular beam epitaxy (MBE) at low substrate temperatures (LT-GaAs buffer) possess unique semi-insulating properties that are useful for elimination of side-gating in MESFETs and HEMTs. They are also useful for ultra-fast optoelectronic switching. However, the mechanism for their semi-insulating properties have not been clarified yet, being disputed between two models, i.e., the deep level compensation model and the As-precipitate-induced Fermi level pinning model.
The purpose of this paper is to investigate deep level properties of LT-GaAs layers by using deep level transient spectroscopy (DLTS) and photocapacitance (PHCAP) techniques. Si-doped conductive LT-GaAs layers were grown at 300-400deg.C so as to directly apply the DLTS and PHCAP techniques to the LT-GaAs layer. Main points are the following:
(1) The LT-GaAs layer was grown by a standard MBE system. The growth temperature (Tg) changed over a range of 250-580deg.C. After the growth, all the samples were annealed at 580deg.C in the MBE chamber under arsenic over-pressure. The conductive layers with a carrier concentration of 1x1016-3x1017 cm-3 were achieved by Si-doping at Tg > 300deg.C, whereas all the layers grown at 250deg.C exhibited semi-insulating property.
(2) Five electron traps were detected by DLTS in the Si-doped LT-GaAs layers grown at 300-400deg.C. The dominant trap was found to be the S1 level whose energy position is Ec-0.64eV. The signature plot of S1 is different from that of EL2, but is similar to those for EB3 and EB4 which are produced by irradiating GaAs epitaxial layer by electron beam. The concentration of the S1 trap rapidly increased as the growth temperature Tg was reduced. On the other hand, the concentrations of other traps remained more or less the same.
(3) Clear photoquenching of capacitance was observed in the Si-doped LT-GaAs layers at temperatures below 110K. The transient was found to follow a simple exponential form. The trap density estimated from the quenched capacitance was in excellent agreement with the density of the S1 level obtained by DLTS measurement. Thus, the S1 trap is responsible for the observed photoquenching behavior, showing that it has a metastable state. This seems to indicate the presence of a large lattice relaxation around the S1 trap.
(4) From the temperature dependence of the thermal recovery rate, the recovery barrier (ER) from the metastable state to the ground state of the S1 trap was estimated to be 0.06eV. This value is much lower than that of the well-known EL2 level (ER = 03.35-0.40eV).
9:40AM, N5
"Deep Level Defects in GaAs/Si Grown by Low Temperature Atomic H-Assisted MBE:" YOSHITAKA OKADA, James S. Harris, Jr, Solid State Electronics Laboratory, McCullough 226, Standford University, Standford, CA 94305-4055; Werner Götz, Xerox Palo Alto Research Center, 3333 Coyote Hill Road, Palo Alto, CA 94304
The practical importance of heteroepitaxy of GaAs on Si substrates has long been recognized. However, several issues in the area of epitaxial growth technology yet remain to be solved and most of all, the reduction of the dislocation density has been the primary target. For this goal, a surfactant epitaxy system was constructed by installing a hydrogen-cracker to the MBE chamber (H-MBE). In the GaAs-on-Si materials grown by H-MBE at a low temperature of ~330deg.C, the dislocation densities were successfully reduced to the 104 cm-2 range as determined from the etch-pit density measurement. In this work, the electrical activity of defects in low dislocation density p+n GaAs diodes grown on Si and GaAs substrates by MBE and H-MBE were characterized by deep level transient spectroscopy (DLTS). In the DLTS measurement, the saturated capacitance transients were digitally averaged over 128 individual traces, and recorded at 2K increments over the temperature range from 120 to 380K, with the temperature held constant to within +/- 0.1K during each data acquisition. The well-known electron traps typical of MBE-grown GaAs, M3 (0.29+/-0.1 eV), M4 (0.46+/-0.1 eV), M6 (0.51+/-0.1eV) and EL2 (0.82 +/- 0.1 eV) were detected in both the heteroepitaxial and homoepitaxial GaAs grown by H-MBE, with no new levels in the upper half of the band gap. The trap densities were significantly reduced for homoepitaxial GaAs grown at 580deg.C and 330deg.C by H-MBE with respect to MBE by a factor of 3 ~ 10 and 1.3 ~ 14, respectively. The trap densities for the GaAs-on-Si grown by H-MBE were in between those of homoepitaxial GaAs by H-MBE and MBE grown at 330deg.C. As additionally important, the reverse saturation current of the diode was reduced as much as by a factor of ~ 17 in the H-MBE sample compared to the MBE at 330deg.C, and also an improvement of a factor of ~ 1.6 was obtained in the H-MBE sample grown at 580deg.C. These results can be explained by the mechanism of in-situ passivation of the defects and impurities responsible for these electron traps by atomic H irradiated during the MBE growth and thus make the H-MBE technique a cost-efficient and technologically advantageous approach in obtaining high-quality GaAs materials grown on Si substrates.
10:20AM, N6
"Geometrical/Material Considerations of Precipitates in LTG GaAs:" J.P.KRESKOVSKY, H.L. Grubin, Scientific Research Assoicates, Inc., P.O. Box 1058, Glastonbury, CT 06033
Early simulations of the electrical properties of LTG GaAs involving planar geometries showed that both Schottky barrier and defect models of precipitates (defects are localized around specific sites with densities within the range of experimental observation), would yield qualitative and quantitative agreement with respect to the dc semi-insulating properties of LTG GaAs.
However, because precipitates are not planar, rather they are confined in three dimensions, a study of confined spherical precipitates was performed. These studies showed that both Schottky barrier and defect models gave qualitatively and quantitatively similar results, but only when the defect densities were well above experimental observation. The preliminary conclusion was that the defect model was not viable.
When examining the photo-response of LTG materials in which localized Schottky barriers were embedded in material that was relatively free of defects, it was speculated that photo-excited carriers would sustain time constants that were dominated by ambipolar diffusion, and that these time constants would be longer than that seen experimentally.
On the basis of the above discussion a model was proposed to explain much of the electrical and optical properties of the LTG GaAs material. This model has as its basis localized Schottky barriers, required for dc semi-insulating properties, surrounded by a homogeneous distribution of defects at experimentally observed levels, for the transient photo-response times.
To determine the efficacy of this model we have continued our studies of spherically symmetric geometries. Transient calculations were performed and demonstrate that short picosecond time scales are accounted for by residual traps in regions surrounding the precipitates, and that these time constants are, as expected, dependent upon the density of traps. The density of traps surrounding the precipitates required to achieve short photo-response times, is at the present uncertain. For one set of trapping times, trap densities of 1018/cm3 are required for picosecond responses. For a second set of trapping times trap densities as low as 1017/cm3 will suffice. These issues, as well as the issue of trap dominated precipitates will also be discussed.
Supported by the Air Force Office of Scientific Research.
10:40AM, N7
"The Role of Point Defects and Arsenic Precipitates in Carrier Trapping and Recombination in LTG-GaAs:" A.J. LOCHTEFELD, M.R. Melloch, E.S. Harmon, J.C.P. Chang, School of Electrical and Computer Engineering, 1285 Electrical Engrg Bldg., Purdue University, West Lafayette, IN 47907-1285
Many groups have investigated carrier recombination in as-grown and annealed GaAs epilayers grown at low substrate temperatures by molecular beam epitaxy. These low-temperature grown (LTG) GaAs epilayers contain arsenic antisites and gallium vacancies. With anneal these point defects form arsenic precipitates. One important application of these LTG-epilayers is as fast photoconductors because of the short carrier lifetimes. Many groups have claimed that the as-grown LTG-epilayers have the shortest carrier lifetimes. In as-grown materials the initial fast transient is due to electrons being removed from the conduction band and holes from the valence band but not necessarily electron-hole recombination. We have investigated LTG-GaAs epilayers with a wide range of excess arsenic concentrations and anneal conditions to study the role of the point defects and arsenic precipitates on the carrier trapping and recombination.
We used a pump/probe differential transmission measurement technique to measure the carrier trapping and recombination. An increase in transmission occurs with the photogeneration caused by the pump pulse because of band filling. A transient in the transmission occurs as these photogenerated carriers recombine or become trapped. If the transient is due to electron-hole recombination, the transmission decays to its equilibrium value, which is what we observe in most LTG-GaAs that has been annealed. For as-grown LTG-GaAs, we see an initial fast transient occurring as the photogenerated carriers are trapped followed by a slow transient. This initial fast transient actually overshoots the equilibrium transmission level to a situation where there is an increase in absorption. This increase in absorption is due to point defects filled with electrons and holes that can now capture photons. This second transient is beyond the upper lifetime measurement limit - 1 nsec - of our pump/probe system. For as-grown epilayers with a sufficiently low concentration of excess arsenic, where we can generate concentrations of electron-hole-pairs comparable to the ionized arsenic antisite concentration, we can observe a two component decay because of fast capture of electrons followed by a slow capture of holes. We estimate the electron capture cross section to be about 200 times larger than the hole capture cross section. In these epilayers, the differential transmission transient becomes single exponential and significantly faster after anneal and formation of arsenic precipitates, indicating the arsenic precipitates have a much larger effective hole capture cross-section than the arsenic antisites.
This work was supported by the US Air Force Office of Scientific Research under Grant No. F49620-93-1-0031 and F49620-93-1-0388, and the NSF under grant DMR-9400415
11:00AM, N8
"Photogeneration, Trapping and Recombination in III-V Semiconductors Grown at Low Temperature:" A.I. LOBAD, G.W. Wicks, P.M. Fauchet, Department of Electrical Engineering, The Institute of Optics, and Department of Physics and Astronomy, University of Rochester, Rochester, NY 14627
When III-V semiconductors are grown at low substrate temperatures (LT III-V), they all exhibit an ultrafast optical response. We have recently shown this to be the case in LT III-Vs such as GaAs, InGaAs, InGaP, and InP, by performing femtosecond time-resolved pump-probe and photoluminescence experiments [1-5]. We have found that the characteristics of the ultrafast optical response depend on a variety of parameters such as growth and annealing conditions and alloy composition and doping. One of the most important discoveries is that the (sub)picosecond response is not always associated with ultrafast recombination of electrons with holes but rather with ultrafast trapping of electrons and/or holes in non-conducting states. In this case, the maximum bit rate at which LT III-V devices can operate may not be set by the trapping time but rather by the recombination time. In some cases, we have found that the recombination time is in the nanosecond range or more. Until now, all these experiments had been performed using above or near band edge light. In this presentation, we report the results of our investigation of the complete excess carrier dynamics, from photogeneration to trapping and recombination, and its relation with the preparation and processing of the LT III-Vs. This study is made possible by the recent availability of femtosecond pulses continuously tunable from the UV to past 10 um, which makes probing of the defect states well below the bandgap of the LT III-Vs possible.
This work was supported in part by an AASERT award from AFOSR.
___________________________________
[1] "Femtosecond Carrier Dynamics In Low-Temperature Grown Ga0.51In0.49P," Y. Kostoulas et al., Appl. Phys. Lett. 67, 3756-3758 (1995).
[2] "The Ultrafast Carrier Dynamics in Semiconductors: The Role of Defects," P. M. Fauchet et al., Mat. Res. Soc. Symp. Proc. 378, 171-176 (1995).
[3] "Femtosecond Carrier Dynamics in Low-Temperature-Grown Indium Phosphide," Y. Kostoulas et al., Appl. Phys. Lett. 66, 1821-1823 (1995).
[4] "Femtosecond Carrier Dynamics in Low-Temperature-Grown III-V Semiconductors, Y. Kostoulas et al., in Ultrafast Phenomena in Semiconductors, SPIE Vol. 2142, pp. 100-109 (1994).
[5] "Femtosecond Optical Response of Low Temperature Grown In0.53Ga0.47As," B. C. Tousley, S. M. Mehtra et al., J. Electron. Mater. 22, 1477 (1993).
11:20AM, N9
"Low-Temperature Grown Semi-Insulating In0.49Ga0.51P Grown by LP-MOCVD:" Q.J. HARTMANN, N.F. Gardner, T.U. Horton, A.P. Curtis and G.E. Stillman, University of Illinois at Urbana-Champaign, Center for Compound Semiconductor Microelectronics and Department of Electrical and Computer Engineering, 150 Microelectronic Laboratory, Urbana, IL 61801
The growth and characterization of semi-insulating (SI) In0.49Ga0.51P grown at low substrate temperature (475deg.C < Tg < 525deg.C) by metalorganic chemical vapor deposition is reported. Although low temperature (LT) grown, high-resistivity InGaP has been reported by GS-MBE, this is the first report of SI-InGaP grown by MOCVD. A high quality semi-insulating epitaxial layer lattice matched to GaAs has many potential applications in GaAs-based devices, including use as a buffer layer in FETs and as a gate material for MISFETs. The only difference in growth conditions between "normal" InGaP (575 deg.C < Tg < 625deg.C) used for the emitter of HBTs and the Si-InGaP described here is the reduced growth temperature.
Several experiments have been performed to characterize this material. All layers are considered lattice matched with [[Delta]]a/a < 1 x 10-3. First, the resistivity of InGaP layers as a function of growth temperature was studied. For all layers grown at or below 525deg.C, the resistivity of InGaP layers as a function of growth temperature was studied. For all layers grown at or below 525deg.C, the resistivity was too high to measure using the Hall effect technique. The resistivity was estimated by sandwiching an undoped LT-grown layer between two n-type InGaP contact layers grown at 575deg.C and then measuring the resistance through the structure. Similar techniques have recently been used to characterize Si-InP.1 The results show that for growth temperatures at or below 525deg.C the resistivity is greater than 1011 [[Omega]]-cm. Double crystal x-ray diffraction of the (004) reflection shows that the structural quality of LT-grown layers is similar to that of conductive layers grown at or above 575deg.C. The 5000 Å thick LT-grown layers are single crystal epitaxial layers with a FWHM of ~ 60 arc sec, comparable to the FWHM of 5000 Å thick layers grown at 575deg.C which range between 40 and 60 arc sec. DLTS measurements show that as the growth temperature decreases to 525deg.C, a broad peak with an ionization energy of ~ .040 eV appears in the spectrum that is not observed in layers grown at or above 575deg.C. This data suggests that a mid gap trap develops during LT-growth that may be responsible for the semi-insulating behavior. Phosphorous anti-site defects with an activation energy of 0.48 eV have previously been suggested to cause the semi-insulating behavior of GS-MBE grown LT-InGaP.2 A decrease in photoluminescence intensity with decreasing growth temperature indicates an increase in non-radiative recombination and supports the DLTS data suggesting an increase in defect concentration with decreased growth temperature. These data indicate that defects incorporated in LT-grown InGaP result in trap concentrations capable of trapping most of the free electrons and cause the material to have a high resistivity. A deficient P concentration at the surface during LT-growth may be responsible for P anti-site defect formation and the semi-insulating behavior.
____________________________________
1) N. F. Gardner et al., Appl. Phys. Lett. 65, 359 (1994).
2) D. C. Look et al., Appl. Phys. Lett. 63, 1231 (1993).
11:40AM, N10+
"Enhanced Superlattice Disordering in Nonstoichiometric Quantum Wells:" I. LAHIRI, J.C.P. Chang, J.M. Woodall, M.R. Melloch, D.D. Nolte, Department of Physics and the MRSEC for Technology-Enabling Heterostructure Materials, 1396 Physics Building, Purdue University, West Lafayette, IN 47907-1396
Anomalous diffusion in undoped low-temperature-grown (LTG) AlAs/GaAs superlattices with extremely low effective migration enthalpies of 0.32 eV have been observed in isochronal rapid-thermal-annealing studies. We propose a new mechanism which utilizes both isochronal and isothermal anneals to recover a migration enthalpy consistent with Ga vacancy diffusion, but with a time-dependent diffusion coefficient expected to be caused by the thermal annealing of the vacancies. For weak anneals these superlattices demonstrate simultaneous ultrafast lifetimes and sharp excitonic features, which are crucial ingredients for photorefractive dynamic holographic devices, electro-optic sampling, ultrafast striplines, ultrafast photodetectors and electroabsorption modulators. However, these advantageous properties degrade rapidly with higher temperature anneals.
Sharp excitonic transitions which yield large electroabsorption, require high-quality quantum-well interfaces. Achieving ultrafast lifetimes in multiple quantum wells combined with sharp excitonic transitions has been an elusive goal. We have demonstrated sharp quantum-confined excitons in ultrafast LTG AlAs/GaAs multiple quantum wells [1] with contrast ratios and linewidths comparable to standard temperature grown (STG) quantum wells. The recombination lifetime for electrons in these samples are significantly shorter than STG quantum wells. The speed-electroabsorption product is currently being investigated as a viable figure of merit.
Enhanced superlattice disordering, probably mediated by arsenic precipitate coarsening, intermixes as well as roughens the well-barrier interfaces. This results in a significant decrease in the electro-optic response of these devices. The anomalously low effective migration enthalpy of 0.32 eV, probably due to nonlinear diffusion, is much smaller than any physically recognized mechanisms, such as the migration enthalpy of 1.7 eV attributed to Ga vacancy diffusion or the activation energy of 0.87 eV due to arsenic precipitate coarsening in LTG GaAs.
____________________________________
This work was supported in part by the MRSEC program of the NSF under award #DMR-9400415. D. D. Nolte acknowledges support by the NSF PYI program. M. R. Melloch acknowledges support from the AFOSR under grant # F49620-93-1-0031.
1) I. Lahiri, D. D. Nolte, E. S. Harmon, M. R. Melloch and J. M. Woodall, Appl. Phys. Lett. 66, 2519 (1995).
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