Sponsored by: EMPMD Thin Films & Interfaces Committee
Program Organizers: N. M. Ravindra, New Jersey Institute of Technology, Newark, NJ; R. K. Singh, University of Florida, Gainesville, FL
Monday, PM Room: Grand J
February 5, 1996 Location: Anaheim Marriott Hotel
Session Chairmen: Arun Nanda, Sematech, Austin, TX; Ahmad Kermani, CVC Products, Inc., Fremont, CA
2:00 pm Invited
MODELING, MEASUREMENT AND CONTROL OF RAPID THERMAL PROCESSING: Krishna C. Saraswat, B. T. Khuri-Yakub, Department of Electrical Engineering, Stanford University, Stanford, CA 94305
A highly flexible Rapid Thermal Multiprocessing (RTM) reactor is described. This flexibility is the result of several new innovations; a lamp system, an acoustic thermometer and a real-time control system. The new lamp has been optimally designed through the use of a "virtual reactor" methodology to obtain the best possible wafer temperature uniformity. It consists of multiple concentric rings composed of light bulbs with horizontal filaments. Each ring is independently and dynamically controlled providing better control over the spatial and temporal optical flux profile resulting in excellent temperature uniformity over a wide range of process conditions. An acoustic thermometer non-invasively allows complete wafer temperature tomography under all process conditions - a critically important measurement never obtained before. For real-time equipment and process control, a model based multivariable control system has been developed.
2:30 pm Invited
RAPID THERMAL CHEMICAL VAPOR DEPOSITION OF SILICON-BASED HETEROSTRUCTURES: James C. Sturm, Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
This talk will describe the use of RTCVD for the growth of silicon-based heterostructures such as Si/Sil-x Gex and SiSil-x-y Gex Cy. Such heterostructures can be used to improve the performance of conventional silicon devices such as MOSFET's and bipolar junction transistors (through heterojunction MOSFET's and heterojuntion bipolar transistors), and also to implement new opto-electronic functions onto silicon such as infrared detectors and emitters. Because of the strain involved in such pseudomorphic structures, the tendency towards three dimensional growth, and the desire for abrupt interfaces on a scale of nm, these structures are typically grown at temperatures below 650[[ring]]C. These low temperatures bring both advantages and disadvantages for RTCVD compared to traditional silicon epitaxy at higher temperature. For example, due to lower growth rates, thermal transients need not be as fast as at higher temperatures, and gas switching of processes can be used instead of temperature switching. However, increased sticking coefficients of impurities cause an increased sensitivity to gas purity. We have found that high quality RTCVD growth of these heterostructues is only possible due to the fortitous effects of hydrogen passivation present during the growth, which can reduce oxygen sticking coefficients several orders of magnitude. There is also a need for more precise temperature measurement because of the stronger dependence of growth rate on temperature, and a non-invasive non-pyrometric method used daily in our lab for accurately measuring the substrate temperature in the reactor in this range will be shown. Finally, the relative technical merits based on fundamental considerations of RTCVD vs MBE and UHVCVD for the growth of these structures will be discussed.
3:00 pm Invited
USING PHOTONIC EFFECTS IN OPTICAL PROCESSING FOR SILICON DEVICE FABRICATION: Bhushan L. Sopori, National Renewable Energy Laboratory, 1617 Cole Boulevard, Golden, CO 80401
Using optical energy for semiconductor processing has many advantages over conventional furnace processing. Some of these advantages, generally made use of in RTA processing, include ability to rapidly increase the wafer temperature, system cleanliness, possibility of excitation from outside the furnace, and low thermal budget. In an RTA process, the light is used to generate heat in the semiconductor wafer, and reactions are thermally activated. Recently, we found that RTA processing can also produce photonic effects that activate several reactions at much lower temperatures as compared to the thermal activation alone. We call this mode of RTA as Optical Processing (OP). We have developed several processes for silicon solar-cell fabrication that can also be used for other semiconductor devices. In general, the photonic phenomenon invoked in OP can produce reactions at the interface(s) of a multilayer device or in the bulk of the semiconductor. Suitable choices of process parameters such as the incident spectrum, light intensity, and the process time can be applied to favor the desired process. The interface- related processes are used to: (1) form very low-resistivity Si-Al ohmic contacts with controlled optical properties at the interface, graded alloy compositions, and textured interfaces for light trapping in solar cells; (2) grow high-quality, thin SiO2 at low temperatures (<500 degrees C), with average growth rates reaching 5 nm/minute. The bulk effects are used for: (1) low-temperature, very rapid gettering of metallic impurities like Cu, Ni, and Fe; (2) impurity/defect passivation of solar cells by hydrogen. OP is a very low thermal budget, low-temperature process that typically uses only 4-6 W/cm2 of broadband incoherent light. Lower temperatures are needed because photonic effects diminish at higher temperatures. Typical process times for the above applications are 60-90s. These features make OP well suited for a variety of commercial applications that require high throughput and continuous or batch processing. This paper will review basic concepts of OP and the operational differences between conventional RTA and OP. We will also describe applications in solar-cell and detector fabrication.
3:30 pm BREAK
3:45 pm
IN SITU ANALYSIS DURING RAPID THERMAL ANNEALING OF THIN FILM REACTIONS IN SUBMICRON CMOS STRUCTURES: L.A. Clevenger, C. Cabral, Jr., R.A. Roy, C. Lavoie, K.L. Saenger, K. Rodbell & J. Jordan-Sweet, IBM, T.J. Watson Research Center, Yorktown Heights, NY 10598; G. Morales, K.L. Ludwig, Jr., Boston University, Boston, Massachusetts 02215; G.B. Stephenson, Argonne National Laboratory, Argonne, IL 60439
The formation of thin film conductors is a critical processing step in CMOS (complementary-metal-oxide-semiconductor) logic and memory device manufacturing. In this work, we have studied the formation of low resistance titanium silicide and Al(Cu,Si)/Ti interconnections used in submicron device structures (0.1 to 1.0 micron in width, 50 to 500 nm in thickness) in situ, during rapid thermal annealing using synchrotron x-ray diffraction analysis on a millisecond time scale. In addition to the collection of x-ray diffraction spectrum, resistance and optical scattering (lambda = 632.8nm) measurements were simultaneously done to gather data on thin film resistance and surface roughness. Our results demonstrate that the formation of the low resistance C54-TiSi2 phase is limited by the submicron linewidth of the silicide structure. For patterned Al(Cu,Si)/Ti conductors, the formation of the conductive AlTi3 intermetallic phase is restricted by the amount of Si in the Al(Cu,Si) thin film.
4:05 pm
SELECTIVE EPI OF SILICON USING RTCVD TECHNIQUES: M.C. Ozturk et.al., Department of Electrical & Computer Engineering, North Carolina State University, Raleigh, NC 27695-7911
Abstract not available.
4:25 pm
EFFECT OF TITANIUM FILM THICKNESS ON SILICIDE FORMATION & KINETIC: S. Sharan, Micron Technology Inc., MS 306, 5683 S Alyssum Pl., Boise, ID 83705; R.K. Singh, R. Nagabhusnam, Department of Materials Science & Engineering, University of Florida, Gainesville, FL 32611
Abstract not available.
4:45 pm
RAPID ELECTRICAL CHARACTERIZATION OF OXIDES AND NITRIDED OXIDES GROWN IN A SINGLE-WAFER REACTOR: J. Sagnes, D. Laviale, France Telecom, CNET-CNS, BP 98, F-38243 Meylan-cedex, France; F. Martin, CEA-LETI/DMEL, BP 85X, F-38041 Grenoble-cedex, France; F. Glowacki, L. Deutschman, AST Elektronik, DaimlerstraBe 10, D-89160 Dornstadt, Germany
Rapid Thermal Oxidation (RTO) and Nitridation (RTN) are performed in a module of a single-wafer cluster tool. The heating in the module makes use of a dedicated lamp array system for uniformity control with processes which can be achieved at atmospheric and low (10^-6 torr) working pressures. Electrical results obtained via a SCA (Surface Charge Analyzer) equipment on thin oxides and NO nitrided oxides (<=6nm total thickness) will be presented. It will be shown that oxides obtained by RTO present a charge density equivalent to that obtained in batch oxidation furnaces as soon as some process conditions are fulfilled. The NO nitridation of the SiO2/Si interface presents different charge states according to the process conditions (temperature, time and working pressure). We will show that after an anneal at low temperature, the initial level of charges is recovered. This work has been carried out within the GRESSI consortium between CEA-LETI and France Telecom-CNET.
5:05 pm
SELECTIVE RTCVD OF TiSi2: M.C. Ozturk et.al., Department of Electrical & Computer Engineering, North Carolina State University, Raleigh,NC 27695-7911
Abstract not available.
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